Applying Two-Pattern Tests Using Scan-Mapping - VLSI Test Symposium, 1996., Proceedings of 14th

This paper proposes a new technique, called scan-mapping, for applying two-pattern tests in a standard scan design environment. Scan-mapping is performed by shifting the first pattern (VI) into the scan path and then using combinational mapping logic to generate the second pattern (V2) in the next clock cycle. The mapping logic is placed in the scan path and avoids the performance degradation of using more complex scan elements to apply two-pattem tests. A procedure is described for synthesizing the mapping logic required to apply a set of two-paiftern tests. Scan-mapping can be used in deteminisl5c testing to apply two-pattern tests that can‘t be applied using scan-shifing or functional justijication, and it can be used in built-in self-testing (BIST) to improve the fault coverage for delay faults. Experimental results indicate that, for deterministic testing, scan-mapping can reduce area overhead and test time compared with using complex scan elements; and for pseudo-random testing, scan-mapping can significantly improve the fault coverage using only a small amount of mapping logic.